Prakash Narain discusses five ways to stop connectivity error escapes while minimizing engineering time.
STMicroelectronics’ case study comparing Cadence Jasper CSR formal app and UVM with Cadence Xcellium for register map verification. Metrics include: Time, code & functional coverage, and bugs found.
Amit shares six fundamental properties of intelligent custom IC verification, including AI technologies, that deliver orders-of-magnitude speedups and productivity improvements to engineering teams.
Samsung Electronics case study on Dynamic CDC verification methodology, comparing design-aware models from Real Intent Meridian CDC with conventional data-transition based models, or simulation alone.
Dean Drako shares insights based on an industry survey on 5 key elements of multisite design & IP management, including IP reuse, design tapeout & resource predication, and cloud trends.
Prakash Narain discusses five DFT verification step required to stop error escapes while maximizing engineering efficiency in tight project windows.
Anirudh Devgan offers his detailed insights on computational software. He shares a clear definition of computational software, along with specific ways it is transforming system design & hardware design.
With 47% of organizations expected to utilize hybrid cloud bursting for design and/or verification in the next two years, Dean Drako shares his principles for successful execution.
Prakash Narain discusses reset domain crossing fundamentals on eliminating bugs, compares RDC to CDC, and the power, performance, and area implications of certain design choices.
Prakash Narain discusses static sign-off fundamentals during the design process, including primary target domains and implementation techniques, plus a comparison of static sign-off vs. simulation & formal.
Comparison of where different video surveillance functions can be located, along with the tradeoffs for each for different scenarios, especially in light of the advent of AI.
