RTL Linting. Enforces coding guidelines and identifies functional issues prior to simulation. Rules cover syntax, semantic, and style checks, to ensure high quality RTL.
Clock Domain Crossing. Structural and functional analysis ensure that signals crossing asynchronous clock domains are received reliably, verifying that the data will be transferred across clock domains without introducing design problems.
Reset Domain Crossing. Confirms that signals crossing reset domains function reliably, identifying metastability problems and glitches arising from software and/or low power asynchronous resets, or re-convergence of synchronized resets.
Power. Ensure that power management is correctly implemented, and power switching will cause the chip to malfunction.
X-Propagation. Performs audit and debug of design initialization to identify potential X-optimism and prevent inaccurate RTL simulation.
Design for Test. Early RTL and netlist analyses are performed to identify all testability violations in a timely and efficient manner before full DFT/ATPG.